To facilitate the operation between various integrated circuits within a system it is common to use synchronous devices which operate synchronously with a system clock. Synchronous devices commonly receive the system clock signal and generate an internal synchronous clock signal from which to time the various functions of the device.
A synchronous circuit is referred to as "self-timed" when its various internal operations follow from an initial system clock edge. To accomplish self-timing it is known in the prior art to generate one or more internal clock pulses from a system clock edge. The internal clock pulses are distributed within the circuit to trigger internal operations. It is particularly advantageous to generate a second clock pulse "within" a first clock pulse; i.e. the first edge of the first clock pulse precedes the first edge of the second clock pulse, while the second edge of the first clock pulse follows the second edge of the second clock pulse. The arrangement of closely-spaced, subsequent clock pulses is useful for closely timed circuit functions.
A prior art self-timed clock pulse circuit is illustrated in FIG. 1 and designated by the general reference character 10. The prior art clock pulse circuit includes a clock edge detector 12, a pull-up circuit 14, a signal delay 16, a pulse edge detector 18, and a pull-down circuit 20. The clock edge detector 12 receives an external clock signal and activates the pull-up circuit 14 when it detects a rising external clock edge. When activated, the pull-up circuit 14 temporarily pulls a clock node 22 to a positive power supply 24. Assuming the clock node 22 was previously at a low logic level, the clock node 22 undergoes a low-to-high transition. This transition functions as the first edge of an internal clock pulse (CLP). The logic transition at clock node 22 is delayed by the signal delay 16 and then applied to the pulse edge detector 18. The pulse edge detector 18, in a similar fashion to the clock edge detector 12, activates the pull-down circuit 20 when it detects a rising clock pulse edge. The pull-down circuit 20, like the pull-up circuit 14, temporarily pulls the clock node 22 to ground 26. This high-to-low transition creates the second clock pulse edge. The clock pulse circuit 10 is then ready to detect the next rising edge of the external clock signal.
A drawback to prior art self-timed clock pulse circuits is the susceptibility of such circuits to a lock-up condition upon power-up. For example, the discussion of the circuit of FIG. 1 assumed that the clock node 22 was low prior to the arrival of the first rising external clock edge. For example, if node 22 was high on power-up, no pulse edge would be generated by the arrival of a rising external clock edge, and clock node 22 would remain high. The clock circuit would be "locked-up" in this state.
It is known in the prior art to overcome the uncertainty of logic states upon power-up by relying upon a circuit which detects the ramp-up of the power supply and generates a particular logic state therefrom. Such circuits can be unreliable, however, by failing in instances where the ramp-up is non-ideal (i.e. too gradual or too fast). Additionally, such circuits can require relatively large circuit components, such as large coupling capacitors.
Accordingly, it would be desirable to provide a self-timed synchronous clock pulse circuit that is immune to a lock-up condition upon power-up without relying upon power supply ramp-up detection circuits.